1. Field of Invention
The present invention relates to a fabrication method of a trenched power metal-oxide-semiconductor field effect transistor (power MOSFET), and more generally to a fabrication method of a trenched power MOSFET which can reduce the MOSFET switching loss.
2. Description of Related Art
A power MOSFET is widely applied to power switch devices such as power supplies, converters or low voltage controllers. Generally speaking, a conventional power MOSFET is usually designed as a vertical transistor for enhancing the device density, wherein for each transistor, each drain region is formed on the back-side of a chip, and each source region and each gate are formed on the front-side of the chip. The drain regions of the transistors are connected in parallel so as to endure a considerable large current.
The working loss of the power MOSFET can be divided into a switching loss and a conducting loss. The switching loss caused by the input capacitance Ciss is going up as the operation frequency is increased. The input capacitance Ciss includes a gate-to-source capacitance Cgs and a gate-to-drain capacitance Cgd. When the gate-to-drain capacitance Cgd is decreased, the switching loss is accordingly reduced, and the avalanche energy is improved under the unclamped inductive load switching (UIS).
Accordingly, how to fabricate a power MOSFET having a low gate-to-drain capacitance Cgd has become one of the main topics in the industry.